Electronic counter



April 17, 1962 R. R. JOHNSON ELECTRONIC COUNTER 2 Sheets-Sheet 1 Original Filed Aug. 11

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United States Patent 3,030,581 ELECTRONIC COUNTER Robert R. Johnson, Palo Alto, Calif., assignor to Hughes Aircraft Company, Culver City, Calif., a corporation of Delaware Continuation of abandoned application Ser. No. 373,558, Aug. 11, 1953. This application July 1, 1958, Ser.

2 Claims. (Cl. 328-43) This invention relates to electronic counters.

This application is a continuation of the earlier filed application of Robert R. Johnson, entitled Shifting Register Counters, filed on August 11, 1953, and bearing Serial No. 373,558, now abandoned.

It is a general object of this invention to provide a novel, inexpensive and reliable high speed electronic counter requiring a minimum of gating elements and comprising a novel combination of a shifting register or delay line and a counting stage.

It is another object of this invention to provide an improved and simplified shifting counter of the character referred to in the previous object and adaptable for counting in any desired mode in a cyclic fashion without resorting to a resetting operation.

It is a further object of this invention to provide a novel and improved electronic pulse counter comprising shifting and counting stages arranged in a recirculating loop for controlling the pulse response sequence of one another.

It is yet another object of this invention to provide an improved electronic shifting counter capable of being sensed for rendering a control indication at any predetermined count within the capacity of the counter.

Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by way of example, the principle of the invention and the best mode, which has been contemplated of applying that principle. Other embodiments of the invention employing the same or equivalent principle may be used and structural changes made as desired by those skilled in the art without departing from the present invention and within the spirit of the appended claims.

In the drawings:

FIG. 1 is a block diagram of the novel electronic counter embodying the invention;

FIG. 2 is a partial block and diagrammatic representation of a novel counter constructed according to the invention; and

FIGS. 3 and 4 are block diagrams of other embodiments of the invention.

Briefly, the invention provides an electronic pulse counter comprising a cascaded arrangement of a shifting stage cooperating with a counting stage and connected in a recirculating loop. The shifting and counting stages each employ switching circuits arranged to simultaneously receive the pulses to be counted. The pulses to be counted are applied to and circuits arranged between each of the switching circuits for controlling same and including an and circuit connected between the serially connected shifting and counting stages. The latter and circuit renders the counting stage responsive to the pulses to be counted only when the final switching circuit of the shifting stage is in a preselected condition. The output condition of the counting stage is in turn arranged to simultaneously control the condition of the first switching circuit of the shifting stage to thereby determine the path of the pulses to be counted through the shifting stage. This latter control is elfected by means including a recirculating loop interconnecting the output of the counting stage with the input to the shifting stage.

3,030,581 Patented Apr. 17, 1962 Referring to the drawings, the novel electronic counter 10 is shown as defined by a shifting stage 11 cascaded or serially arranged with a counting stage 12 interconnected by means of a lead wire 13 into a recirculating loop. A source of pulses 14 providing the pulses to be counted is shown coupled in parallel with the shifting stage 11 and the counting stage 12 to simultaneously receive the pulses therefrom.

The shifting stage 11 and the counting stage 12 each comprise switching circuits such as the switching circuit A, shown in FIG. 2 as a conventional bistable or flip-flop circuit. A typical circuit of this type comprises two triodes such as the triodes 15 and 16 connected together so that one is always conductive and the other non-conductive to thereby define the two stable states. The two tubes 15 and 16 are arranged in the usual fashion with cross coupling networks interconnecting the plate and grid circuits of the tubes 15 and 16. These networks comprise the parallel arrangement of a resistor and capacitor such as the resistor 17 and capacitor 18 illustrated. The switching circuit A, as will be seen from the examina tion of FIG. 2, in all other respects is symmetrical so that either tube 15 or 16 may be conducting. This type of bistable circuit has two static complementary output signals which are identified as the signals A and A, one signal being derived from the plate of each tube. The signal A is derived from the plate of tube 15 while the signal A is derived from the plate of the tube 16. The input signals to the bistable circuit A are controllably delivered to the grid of either the tube 15 or the tube 16 by means of the corresponding input leads identified as the one input or the zero input. The one input is connected to the grid for the tube 15 while the zero input is coupled to the grid for the tube 16.

Each of the input circuits one and zero for the bistable circuit A are controlled by an individual two input and circuit or gate, respectively identified as the and circuits 20 and 21. The and circuit 20 may be any conventional and circuit known in the art and in this instance is schematically represented by a pair of similarly poled diodes 22 and 23 and which diodes are shown with their cathodes adapted to be connected to a source of a positive potential by means of a dropping resistor 24. The anodes of the diodes 22 and 23 are connected to provide the two input leads for the and circuit 20. The and circuit 20 operates in the conven tional fashion, namely, an output signal will be delivered to the one input of switching circuit A when a signal is simultaneously present at the cathodes of both diodes 22 and 23. The and" circuit 21 and the remaining and circuits employed in the counter 10 are similarly arranged and are symbolically represented in the same fashion as the and circuit 21. Also, the remaining switching circuits, identified as the switching circuits B and C for the switching stage 11, are shown in block form with the one and zero inputs and the complementary outputs such as the outputs B and ii for the circuit B are shown in block form. The switching circuits B and C are both similarly arranged with an and circuit connected to control each of the one and zero inputs for these circuits. The and circuit 25 controls the one input for circuit B while the and circuit 26 controls the zero input for this circuit. Both the gates 25 and 26 are arranged to simultaneously receive a pulse from the pulse source 14 by means of a lead wire 27. The remaining input for the two-input circuit 25 is provided by the A output of the switching circuit A while the remaining input for circuit 26 is derived from the K output of circuit A.

In this same fashion, the B output of the switching circuit B is directly connected to the an circuit 28 for the one input of switching circuit C while the F output is directly connected to the and circuit 29 controlling the zero input of the C circuit. Each of the and circuits 2'8 and 29" are also arranged to receive simultaneously a pulse from thepulse source 14 by means of the lead wire 31.

The counting stage 12, in this instance, is shown as a single switching circuit D having one and zero inputs and D and D outputs. The counting circuit D has both its one and zero inputs controlled by a s'ingle twoinput and circuit32 and which and circuitis respon sive. to the simultaneous presence of a signal from the C output of circuit C and a pulse tobe counted from the source 14 coupled thereto by means ofthe lead wire 33. The and circuit3'2 controls the countingcircuit D upon a signal being delivered thereto to change. the state of the circuit to its opposite. stable state; that is, if the output D is high and D is low and a signal is, delivered from thecircuit 32, the counting, circuit D will be set with the D output high and the D output low. 7

The pulse source 14 is also coupled to one of theinputs for each of the input and circuits 2 and 21 of the shifting stage 11 by meansof a lead wire 34. The pulsesin this fashion are delivered simultaneously to each of the switchi'ngcircuits comprising the shifting stage 11 and. the counting stage 12. The remaining inputs for the and circuits and 21 are respectively connected with the D and. D" outputs of. the switching circuit D from counting. stage 12. In thisfashion, theshifting stage 11 and the: counting stage 12 are connected in a recirculating or regenerativeloop so that the output condition of the switchingcircuit D is registered or. stored in the circuit A upon. the coincidental arrival ofa pulse from the source 14 at eitherot the circuits 201 or 21.

The simultaneous switching of the switching circuits A and D in response to apulse to be counted obviates the time delay to propagate a carry from the circuit D to the circuit A- This simultaneous switching feature. as applied to counters is described and claimed more fully in a copending application of Eldred C. Nelson, entitled High Speed Flip-Flop Counter, fi led on September 10, 1951, Serial No. 245,860, and assigned to the same as signee as this application.

It will now be appreciatedfrom the above description that the switching circuits A-C are arranged in a parallel shift register configuration. The input circuit of this shift register is controlled by the output condition of the associated counting stage to thereby determine the path of a pulse to be counted through the shift register. It is also seenthat only the one input signals registered in the C switching circuit are registered in the counting stage.

The operation of this novel counter 10 will now be explained in connection with FIG. 2' and Chart I.

Chart I V H Switching Circuits Pulses to be Counted A B C D QHHOHQHHHHOOOHOO As it will be noted from the above chart, the counter 10 is a scale of 15 counter and is initially arranged with the switching circuit A in the one stage while the remaining switching circuits B, C and D are arranged in the zero stage. The one and zero notation in Chart I is intended to indicate that a switching circuit in the one state has its corresponding output high and the complementary output low, for example, the switching circuit A initially has its A output high and the complementary K output low. Since the switching circuits A, B and C are arranged as a shift register, the first two pulses to be counted will merely shift the initial one state of switching circuit A to switching circuit C. Also, since the counting stage Dis in the zero state, the first two pulses are shifted through the shifting stage has zeros. The third pulse to be counted will be etfective to switch the C circuit to the zero state and int-urn thecounting circuit Dwill register a one.

The onefstored in the, counting stage D isindicated by a high output signal at the D output so that upon the arrival of the fourth pulse to be counted, at one will be registered in the A circuit, as a result of the storage condition. of the D circuit being recirculated to the A circuit, rather than a zero as in the previous instances. A one will continue to be registered. in the switching'circuit A inresponse to. the pulses to be counted as long as the D circuit rerriainsin this state as indicated in thechart in response to the fifth and sixth pulses. The

pulses previously stored in the A circuit are in turn shifted to the B and C flip-flopsv so that afterthe arrival of the sixth pulses, all circuits are in the one state. The rival of the seventh pulse changes the state of the D cii' cuit back to the zero state while the ones registered in the other circuits. are shifted one position to the right. In this same fashion, the counter 10 will respond to the pulses to be counted and follow the sequence indicated in Chart I until. the arrival of the fifteenth pulse which sets the counter in the 1000 configuration and which con.- figuration corresponds to the initial or zero state of the counter. The arrival of the sixteenth pulse will then cause the counter 10 to go through another sequence similar to the sequence shown in Chart I. It should be noted that this counter follows the same sequence automatically and resets itself without any special provisions therefor.

Now referring to FIG. 3, a scale of 31 counter of generally the same configuration as the counter of FIG. 2, will be described. The chief characteristic of this scale of 31 counter is the utilization of a pair of switching circuits shown as the switching circuits D and E for the counting stage 12 rather than a single switching circuit as shown in the previous embodiment. The switching circuits A-C comprise the shifting stage 11 as in the previous embodiment and are controlled in the same fashion.

The output signal derived from the shifting stage 11 is utilized to control both the switching circuits D and E in this embodiment. Alternatively, the C output is connected to the and circuit 32 controlling both the input leads for the D circuit and is also coupled to input lead of an and circuit 40 connected to control the zero input lead for the switching circuit E. The one input circuit for switching circuit E is provided with a separate and circuit 41 and which circuit is connected to the D output of switching circuit D along with a connection to. the source 14, by means of the lead wire 42. The pulses to be counted from the pulse source 14 are also applied to the and circuit 40 by means of the lead wire 42. It will be noted that the D output circuit is not utilized. in this embodiment and that the E and E ouputs are coupled back to control the one and zero inputs, respectively, for switching circuit A.

The operation of this scale of 31 counter is generally the same shifting and counting action as described in con the counter and which means comprises, in this instance, a comparison circuit shown in dotted outline and identified by the reference character 55. The comparison circuit 55 is arranged to sense when each of the switching circuits 5 A-F are in a zero state corresponding to the time interval when a complete counting cycle has occurred. This indication is provided by means of a six-input and cir- As a result m.m.ma .mm n .mm F r m c N c m P a t r ch u u T e l t n C s E 6 1 m a d u w C A m W m m 00000101O100110O100010010110110001110100001101011100111101111100 S i .1 D e o "o e wfl c M O S a g mu F m 0000101010011001000100101101100011101000011010111001111011111000 mmmc mmmc on w a f 6 6 P C. B d w s M n t a a .1 r A t a p n c t 0 m one .flnnw M m u .1 h n u e e C n P 1 S W t a Cm S n 0 m h wm I n We w vf un ci e m u n A I 1 a gt t f. t H y C i U 0 m .1 r. e e n P u m X a h u .1 c t c d O n t d t u r n mm ouwm C I e e 0 UL. e M m .W e m 2 e w mm B u m 6 Ct 1h 0 T l m A 6 t W. W W T u P h w t u o e s u u m n m t m a o e w n swmm m m n IL t O w W n a m e m m h m umh o I. I. emulated iniz 2 9& 2 Ca m. C a S a O V W n O mmwmllmwm 23333333 3444 .ovo fiw 5 0 5 0 5 0 5 n D an t d a m n m C a a w Switching Circuits Chart II Pulses To Be Counted junction with FIG. 2 as will be apparent from an examination of Chart II below.

Now referring to FIG. 4, a scale of 63 counter utilizing five switching circuits in the shifting stage 11 and a single switching circuit for the counting stage 12 will be ex- The shifting stage -11 is arranged as in the previous embodiment and the additional shifting circuits shifting stage are controlled. The and circuit 46 controls the one input while the and circuit 47 controls the zero input for switching circuit D while the circuits 48 and 49 respectively control the one and zero inputs for switching circuit E. The C output is connected to the remaining input for the and circuit 46 while the 6 output is connected to the remaining input of and circuit 47 and the D and I5 outputs are similarly arranged with and circuits 48 and 49. In addition, these two-input and circuits receive a pulse to be counted from the source 14 by means of the lead wire 51 connected to the circuits 46 and 47 and the lead wire 52 connected to the circuits 48 and 49.

The output of shifting stage 11 is provided by the signal derived from the I? output of switching circuit E and which signal is coupled into and circuit 53 controlling both the one and zero inputs of counting circuit F. The pulses to be counted are also applied to the and circuit 53 by means of a lead wire 54 coupled to the source 14. The control afforded by the single and plained. The general principle of operation of this counter is similar to the operating principles of the previous embodiments, however, this embodiment is arranged with its initial or zero condition so that all the switching circuits are in the zero state. In addition,

circuit shows means for sensing or indicati counter is registering a preselected count as will be explained immediately hereinafter.

are provided with individual and circuits 46, 47

49 for controlling their one,and zero inputs in the same manner as the remaining switching circuits of the As indicated in Chart III hereinabove, the initial condition of the switching circuits A-F comprising the novel circuit 53 causes the circuit F to be complemented with each output signal received from circuit 53. The F and F outputs of the counting circuit F are fed back to the one and zero outputs of shifting circuit A through scale of 63 counter is Set in the slam their respective and circuits 20 and 21. of this initial setting, the first pulse to be counted, derived An important feature of this embodiment is the means rom the Source 14 and pp to the Switching ciIcuit for sensing a predetermined configuration or count of A, will be stored in circuitA as a zero since the F output is high. Also, since the T5. output is high, the first pulsev arriving at an circuit 53 will set switching ctr-- cu'it F to the one stat, and the corresponding F output will be high. As in the previous embodiments, all of the, switching circuits switch simultaneously and the,stor-- age condition'of the counting stage 12 is recirculated baclc to. control the input to the shifting stage 11 so. that the. one state of shifting circuit F is registered in circuiti A; upon the arrival of the second pulse to be counted. The: second pulse to becounted also, shifts the storage condition of circuits A-E one position to the right in response to the pulses to be counted and at this time leaves circuits; B-E- in the zero state. The and circuit 53 is arranged. to complement the switching circuit F when its input con-- dit'ions are satisfied and since the circuit E is in the.zero.- state, the counting stage P will" be switched to the zeroi state in response to-thesecond pulse to be counted.

' An examination of Chart III shows that the storage condition of switching circuit F is regenerated at the circuit A in this same fashion and the condition of circuit P will be complemented or changed each time a pulse to be counted arrives at the and circuit 53 and finds switching circuit E in the z ero state. Accordingly, the counts from the third pulse to the 63rd will cause the counter to assume the configurationsnoted in Chart III and the 63rd pulse will return each of the circuits A E to the zero state completing a counting cycle. At this time, each of the outputs K-F are in the high condition and an output signal will result at the C output of-comparison circuit 55.

It should be noted that an indication or, the count configuration of anypreselected countof the counter may be sensed in addition to the sensing of a complete counting cycle. That is, any count within the capacity of the counter may be indicated by an appropriate sensing circuit. For example, in the counter under consideration wherein the counter sequences through 63. separate counting steps and an output indication is desired when the 30th pulse has been counted, an output indication may be obtained by means of the comparison circuit 55. This output indication is provided by presetting the switching'circuits A-E so that their initial condition is set to a count of 33 (63 minus 30) or 011101, as may be checked in Chart IIIv hereinabove. Accordingly, after 30 pulses have been; counted by the counter preset in this configuration, each of the switching circuits will be set in the zero state and an output indication will be provided at the output circuit C In this same fashion, any other count may be sensed.

Other forms of comparison circuits other than the circuit 55 may be utilized with the counters of thisinvention. For example, a serial operating comparison circuit such as the circuit described and claimed in the copending application of R. R. Johnson, entitled Electronic Magnitude Comparator, Serial No. 394,441, filed on November 25, 1953, and assigned to the same assignee as this application, may be utilized. The sensing circuit may also be arranged to be responsive to preselected signals from the counter rather than all signals and which preselected signals are characteristic of a single count.

It will also be recognized by those skilled in the art that the shifting stage 11 may be any well-known shift register, such as a magnetic core register, or any wellknown delay line such as a sonic delay line or a magnetic drum circulating register. Furthermore, the counter principle may be employed to count time periods as well as pulses. A combination of these basic counters connected in series may be organized to define a counter of any desired capacity. For example, two single flip-flop V counters may be operated simultaneously to provide a counter has been disclosed and which disclosure has advanced the state of the art.

What is claimed is:

1. An electrical counter circuit, comprising: an electrical signal-switching circuit including a plurality of bistable electrical devices each hawing a pair of input circuits and a pair of output circuits, respective gate circuits interconnecting the output circuits of one bistable device with the corresponding input circuits of a succeeding bistable device to serially interconnect said bistable devices; a second electrical signal switching circuit including 'at least one bistable electrical. device having a pair of input circuits and a pair of output circuits; a gate circuit connecting one output circuit. of the last of said serially connected bistable devices of said first mentioned electrical signal switching circuit with both input circuits of said bistable device of said second electrical signal switching circuit; respective gate circuits connecting the output "circuits of said bistable device of said second electrical :slgnal switching circuit with the corresponding input circuits of the first bistable device of said first mentioned electrical signal switching circuit; and an electrical signal circuit, producing electrical pulses to be counted, connectedto each gate circuit.

2. An electrical counter circuit, comprising: an electrical signal switching circuit including a plurality of bistable electrical devices each having respective 1 and 0 representing input circuits and l and 0 representing output circuits, respective gate circuits connecting the l and 0 representing output circuits of one bistable electrical device, with the 1 and 0 representing input circuit, respectively, of a succeeding bistable electrical device; a second electrical. signal switching circuit including at least one bistable electrical device having respective l and 0 representing input circuits and respective l and 0 representing output circuits; a gate circuit connecting the 1 representing output circuit of the last of said. serially connected bistable devices of said first mentioned electrical signal switching circuit with both input circuits of said bistable electrical device of said second electrical signal switching circuit; respective gate References Cited in the file of this patent UNITED STATES PATENTS 2,542,644 Edson Feb. 20, 1951 2,615,127 Edwards Oct. 21, 1952 2,806,947 MacKnight Sept. 11, 1957 2,819,840 Huntley et al. Jan. 14, 1958 2,853,238 Johnson Sept. 23, 1958 2,951,230 Cadden Aug. 30, 1960 

